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Noble approach for mask-wafer measurement by Design-based metrology integration system

机译:基于设计的计量集成系统进行掩模晶圆测量的高尚方法

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OPC technique is getting more complicated toward 32nm and below technology node, i.e. from moderate OPC to aggressive OPC. Also, various types of phase shift mask have been introduced, and then the manufacturing process of them is complicated now. In order to shorten TAT (Turn around time) time, mask technique need be considered in addition to lithography technique.Furthermore, the lens aberration of the exposure system is getting smaller, so the current performance of it is very close to the ideal. On the other hand, when down sizing goes down to 32nm technology node, it starts to be reported that there are cases that size cannot be matched between a mask pattern and the corresponding printed pattern. Therefore, it is very indispensable to understand the pattern sizes correlation between a mask and the corresponding printed wafer in order to improve the accuracy and the quality, in the situation that the device size is so small that low k1 lithography had been developed and widely used in a production.Then it is thought that it is one of the approaches to improve an estimated accuracy of lithography by using contour that was extracted from mask SEM image in addition to mask model.This paper describes a newly developed integration system in order to solve issues above, and the applications. This is a system which integrates CG4500; CD-SEM for mask and CG4000; CD SEM for wafer; using DesignGauge; OPC evaluation system by Hitachi High-Technologies.It was investigated that a measurement accuracy improvement by executing a mask-wafer same point measurement with same measurement algorithm utilizing the new system. At first, we measured patterns described on a mask and verified the validity based on a measurement value, picture, measurement parameter and the coordinate. Then create a job file for a wafer CD-SEM using the system so as to measure the same patterns that were exposed using the mask. In addition, average CD measurement was tried in order to improve the correlation.Also, in order to estimate very accurate pattern shape, a contour was calculated from a mask SEM image, the result and the design data was used in a litho simulation. This realizes verification including mask error.It is thought that it is beneficial for both mask maker and device maker to use this system.
机译:对于32纳米及以下的技术节点,OPC技术正变得越来越复杂,即从中等OPC到积极的OPC。另外,已经引入了各种类型的相移掩模,因此它们的制造工艺现在变得复杂。为了缩短TAT(时间转换)时间,除了光刻技术外,还需要考虑掩模技术。 此外,曝光系统的镜头像差越来越小,因此其当前性能非常接近理想值。另一方面,当缩小尺寸下降到32nm技术节点时,开始有报道说在掩模图案和相应的印刷图案之间存在尺寸无法匹配的情况。因此,在器件尺寸非常小以至于已经开发并广泛使用低k1光刻的情况下,了解掩模和相应的印刷晶圆之间的图案尺寸相关性以提高精度和质量是非常必要的。在生产中。 因此,人们认为这是除了掩模模型之外,还通过使用从掩模SEM图像中提取的轮廓来提高光刻估计精度的方法之一。 本文介绍了为了解决上述问题而开发的集成系统及其应用。这是一个集成了CG4500的系统;掩模和CG4000的CD-SEM;晶圆的CD SEM;使用DesignGauge;日立高科技的OPC评估系统。 研究了通过使用新系统以相同的测量算法执行掩膜晶圆相同点测量来提高测量精度。首先,我们测量了在掩模上描述的图案,并根据测量值,图片,测量参数和坐标验证了有效性。然后使用该系统为晶圆CD-SEM创建作业文件,以测量使用掩模曝光的相同图案。另外,尝试了平均CD测量以改善相关性。 另外,为了估计非常准确的图案形状,从掩模SEM图像计算出轮廓,将结果和设计数据用于光刻模拟中。这实现了包括掩膜错误的验证。 据认为,对于掩模制造商和设备制造商而言,使用该系统都是有益的。

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