The clock distribution network generates and distributes clock signals across the design and it is critical for performance, while consuming a significant portion of the total power. Uncertainties in the clock network delays can reduce performance, yield and may cause functional failures. Several process, environment and temporal variations like gate length variation, density dependent metal thickness variation, IR drop and Negative Bias Temperature Instability (NBTI) can contribute to clock uncertainty or skew. A balanced clock tree structure is used for low power and to minimize variations. Power is further reduced with extensive use of clock gating and using static and dynamic power management. Designs also optimize power by implementing multiple clocks running at different frequencies to meet frequency and power targets. The talk will focus on challenges and solutions in the design and analysis for clock trees to meet performance, power goals and robustness to process variations.
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