Design integration, DFT, and verification methodology for an MPEG1/2 audio layer 3 (MP3) SoC device

摘要

This paper describes the SoC design and integration methodology ofa MPEG1/2 Audio Layer 3 (MP3) decoder chip. Due to a very tightdevelopment cycle we decided to use state of the art methodology forintegration, verification, and design for test (DFT) in order tominimize risk and problem areas. The combination of a top-downintegration flow, strong focus on constraint driven timing analysis, amodular simulation environment, and leading edge DFT solutions led to animplementation cycle of only 8 weeks. The chip is realized in an 0.18μm technology using 5 layers of metal, achieving a final die size of16 mm². The central processor runs at a minimal speed of 140MHz