Design validation of behavioral VHDL descriptions for arbitrary fault models

摘要

In this paper we present a flexible automatic test generation framework to detect a variety of design faults in systems with behavioral VHDL descriptions. Predefined fault models may range from the commonly used state coverage and transition coverage models to any other fault models which can be described as a set of non-linear constraints on the system's behavior. The test generation problem is formulated as a constraint logic programming problem (CLP) and an industrial CLP engine is used to solve it.