This paper proposes a novel method for efficient realization of parity prediction functions in FPGAs. Improving FPGA efficiency can improve the cost/logic ratio, which may allow FPGAs to be used in more application areas. Using ESOP (exclusive-sum-of-products) to represent logic functions often requires fewer product terms than traditional SOP (sum-of-products) methods. Since FPGA logic functions are implemented based on the number of inputs required, rather than complexity of gates, reducing the number of product terms/literals can produce savings. Commercial EDA tools are suboptimal when it comes to synthesizing logic functions into FPGAs. Our results show that our algorithm improves both area and performance metrics. It is believed that our algorithm will also improve FPGA efficiency in implementing arithmetic circuits, error correcting/detecting circuits, and any other XOR-intensive function. Our proposed method, ExorBDS, uses a stage of ESOP minimization, followed by a stage of decomposition using binary decision diagrams (BDDs). Experiments were conducted on 14 MCNC benchmark circuits. The combination of ESOP minimization and BDD-based decomposition showed superior results to that of just using ESOP minimization or BDD-based decomposition in isolation. The results, when compared with commercial EDA tools, are encouraging. On average, our method uses 36.85% of the number of LUTs (look-up tables), has 87.11% of the maximum combinational path delay, and has 26.16% of the area-delay product
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