首页> 外国专利> LOGIC SYNTHESIZER, LOGIC SYNTHESIS METHOD, COMPUTER READABLE RECORDING MEDIUM HAVING LOGIC SYNTHESIS PROGRAM AND STORED THEREIN METHOD FOR MANUFACTURING CIRCUIT

LOGIC SYNTHESIZER, LOGIC SYNTHESIS METHOD, COMPUTER READABLE RECORDING MEDIUM HAVING LOGIC SYNTHESIS PROGRAM AND STORED THEREIN METHOD FOR MANUFACTURING CIRCUIT

机译:具有逻辑合成程序的逻辑合成器,逻辑合成方法,计算机可读记录介质及其存储方法

摘要

PROBLEM TO BE SOLVED: To suppress the formation of a critical path and to reduce a chip area. SOLUTION: This logic synthesizer is provided with a subdividing means 111 for subdividing a module defined within a hardware function description by respective functions and generating subdivided modules, a hierarchizing means 112 for converting the hardware function description to two hierarchies, a rearranging means 114 for rearranging the subdivided modules in the direction of reducing bypass wiring and long distance wiring, a grouping means 115 for grouping the rearranged subdivided modules based on the prescribed condition that a virtual wiring model functions and generating an intermediate hierarchy within the hardware function description converted to the two hierarchies and a synthesizing means 116 for performing a logic synthesis processing to the hardware function description in which the intermediate hierarchy is generated.
机译:要解决的问题:抑制关键路径的形成并减小芯片面积。解决方案:该逻辑合成器具有用于将硬件功能描述中定义的模块按各个功能细分并生成细分模块的细分装置111,用于将硬件功能描述转换为两个层次结构的分层装置112,用于重新布置的重新布置装置114在减少旁路布线和长距离布线的方向上的细分模块,分组装置115,用于基于虚拟布线模型起作用的规定条件对重新布置的细分模块进行分组,并在硬件功能描述内生成转换为两者的中间层级层次结构和合成装置116,用于对生成中间层次结构的硬件功能描述进行逻辑综合处理。

著录项

  • 公开/公告号JP2001188817A

    专利类型

  • 公开/公告日2001-07-10

    原文格式PDF

  • 申请/专利权人 TOSHIBA CORP;

    申请/专利号JP19990375858

  • 发明设计人 SHIMAZAWA TAKAMI;

    申请日1999-12-28

  • 分类号G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-22 01:27:19

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