Hardware software co-synthesis involves determining the hardware and software architectures for an application. This process involves selection of processing elements, mapping application parts to those processing elements followed by scheduling. Various heuristic based co-synthesis algorithms have been proposed but many of them are limited by simple architecture and non-pipelined implementations. In this paper we present a new processor allocation and pipelined algorithm which can be used for hardware software co-synthesis. The algorithm iteratively selects processing elements based on performance improvement and then allocates tasks and creates pipeline stages. Task allocation and pipelining processes are interleaved which helps to remove redundant pipeline stages. The algorithm is also applied to an example task graph and results are discussed
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