The next-generation, digitally controlled DC-DC converters require a high frequency, high resolution, low power and area efficient digital pulse width modulator (DPWM). This paper introduces a self-calibrated segmented DPWM that uses a delay-locked loop to calibrate adjacent delay segments. An 8-bit prototype designed in a 0.13-μm CMOS process operates at a switching frequency of 11.6 MHz, draws 190μA from a 1.2 V supply and occupies only 0.0075 mm2.
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机译：下一代数字控制DC-DC转换器需要高频，高分辨率，低功耗和面积有效的数字脉冲宽度调制器（DPWM）。本文介绍了一种自我校准的分段DPWM，它使用延迟锁定环路来校准相邻的延迟段。一个采用0.13μmCMOS工艺设计的8位原型，其开关频率为11.6 MH z ，从1.2V电源中汲取190μA电流，仅占用0.0075 mm 2 。
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