Performance evaluation of three memory sense amplifiers with input offset cancellation

摘要

The input offset in memory sense amplifiers is a critical parameter that contributes to the practical lower limit on the strength of the differential-mode bitline signals that can be sensed reliably. A typical rule of thumb is that random input offsets of up to 40 mV can be expected in sense amplifiers as a result of inevitable device parameter variations. A related rule of thumb is that the bitline signals should be no less than 100 mV to be reliably sensed in the presence of memory array noise, cell charge leakage, and other inevitable error sources, including the input offset of the sense amplifier. A primary cause of input offset are differences between the device parameters of the main, supposedly matched, sensing transistors. We report the results of a simulation study that determined the dependence of the input offset against mismatch in the threshold voltage of the sensing. transistors. Assuming transistor models from a 180 nm CMOS logic technology, we compared the conventional latch-type sense amplifier with three input offset cancelling sense amplifier designs that were proposed by S. Suzuki and M. Hirata (see IEEE J. of Solid-State Circuits, vol.SC-14, no.6, p.1066-70, 1979), T. Furuyama et al. (see IEDM, p.44-7, 1981), and Y. Watanabe et al. (see IEEE J. of Solid-State Circuits, vol.29, no.1, p.9-13, 1994).