Efficient cryptographic hardware using the co-design methodology

摘要

Most cryptography systems are based on the modular exponentiation to perform the nonlinear scrambling operation of data. It is performed using successive modular multiplications, which are time consuming for large operands. Accelerating cryptography needs optimising the time consumed by a single modular multiplication and/or reducing the total number of modular multiplications performed. We exploit the codesign methodology to engineer a cryptographic device that accelerates the encryption/decryption throughput without requiring considerable hardware area.