A hardware cryptographic engine (8) comprises a direct-memory-access (DMA) input module (13) for receiving input data over a memory bus, and a cryptographic module (15). The cryptographic module (15) comprises an input register (20) having an input-register length, and circuitry (22) configured to perform a cryptographic operation on data in the input register (20). The hardware cryptographic engine (8) further comprises an input-alignment buffer (16) having a length that is less than twice said input-register length, and alignment circuitry (23) for performing an alignment operation on input data in the input-alignment buffer(16). The hardware cryptographic engine (8) is configured to pass input data, received by the DMA input module (13), from the memory bus (10) to the input register (20) of the cryptographic module (15) after buffering an amount of input data no greater than the length of the input-alignment buffer (16).
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