首页> 外文会议>Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on >Fast elliptic curve cryptographic processor architecture based on three parallel GF(2/sup k/) bit level pipelined digit serial multipliers
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Fast elliptic curve cryptographic processor architecture based on three parallel GF(2/sup k/) bit level pipelined digit serial multipliers

机译:基于三个并行GF(2 / sup k /)位级流水线数字串行乘法器的快速椭圆曲线密码处理器体系结构

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Unusual processor architecture for elliptic curve encryption is proposed in this paper. The architecture exploits projective coordinates (x=X/Z, y=Y/Z) to convert GF(2/sup k/) division needed in elliptic point operations into several multiplication steps. The processor has three GF(2/sup k/) multipliers implemented using bit-level pipelined digit serial computation. It is shown that this results in a faster operation than using fully parallel multipliers with the added advantage of requiring less area. The proposed architecture is a serious contender for implementing data security systems based on elliptic curve cryptography.
机译:本文提出了一种不寻常的椭圆曲线加密处理器架构。该架构利用投影坐标(x = X / Z,y = Y / Z)将椭圆点运算所需的GF(2 / sup k /)除法转换为几个乘法步骤。该处理器具有三个使用位级流水线数字串行计算实现的GF(2 / sup k /)乘法器。结果表明,与使用完全并行乘法器相比,这种方法运算速度更快,并且具有占用面积较小的优点。所提出的体系结构是实现基于椭圆曲线密码学的数据安全系统的重要竞争者。

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