面向椭圆曲线密码的处理器并行体系结构研究与设计

摘要

Based on the analysis of the ECC algorithms processing structure characteristics and parallel schedule on finite field level, a parallel architecture processor model for ECC was proposed which adopting the ILP and DLP. A prototype has been implemented based on the parallel architecture processor model. And storage structure in the model is also analyzed. The prototype is realized using FPGA, and synthesis, place and route have been accomplished under 0.18μm CMOS technology. The results prove that the proposed parallel architecture processor for ECC can guarantee high flexibility for arbitrary ECC algorithms and can achieve high performance.%在研究椭圆曲线密码算法的处理特征以及有限域层上的并行调度算法基础上,采用指令级并行和数据级并行方法,提出了面向椭圆曲线密码的并行处理器体系结构模型,并就模型的存储结构进行了分析.基于该模型实现了一款验证原型,在FPGA上成功进行了验证测试并在0.18μm CMOS工艺标准单元库下进行逻辑综合以及布局布线.实验证明提出的并行处理器体系结构既能保证椭圆曲线密码算法应用的灵活性,又能够达到较高的性能.