This paper describes a process for plating of interconnects for advanced electronic modules. In contrast to traditional chemical mediation of plating processes, this process is electrically mediated and does not rely on difficult to control brighteners/levelers. The methodology for selection of the electric mediation p; rameters is based on considerations of mass transfer and microprofiles/macroprofiles related to current distribution. This paper builds on earlier work by incorporating plating cell/tank design issues including air agitation, eductor agi ation, eductor orientation, back and forth panel, movement and knife-edge panel movement. Data for plating industry test panels containing microvias and PTHs of approximately 4:1, 10:1, and 20:1 aspect ratios are presented.
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