首页> 外文会议>International conference on ASIC;ASICON 2001 >High-speed Parallel Multiplier with Redundant-code Algorithm Using Multiple-Valued MOS Current-Mode Circuits
【24h】

High-speed Parallel Multiplier with Redundant-code Algorithm Using Multiple-Valued MOS Current-Mode Circuits

机译:使用多值MOS电流模式电路的冗余码算法高速并行乘法器

获取原文

摘要

A multiple-valued current-mode MOS integrated circuit is proposed for high-speed arithmetic systems at low supply voltage. Since a multiple-valued source-coupled logic circuit with dual-rail complementary inputs results in a small signal-voltage swing while providing a constant driving current, the switching speed of the circuit is improved at low supply voltage. As an application to arithmetic systems, a high-speed parallel multiplier using booth-encoded algorithm and redundant code (which is realized by using multiple-valued MOS Current-Mode circuits) is designed. The performance of the proposed circuits is evaluated to be faster than that of a corresponding binary implementation under the normal power dissipation. A prototype chip is fabricated to confirm the basic operation of the multiple-valued arithmetic circuit.
机译:针对低电源电压下的高速运算系统,提出了一种多值电流模式MOS集成电路。由于具有双轨互补输入的多值源耦合逻辑电路在提供恒定驱动电流的同时,信号电压摆幅较小,因此在低电源电压下电路的开关速度得以提高。作为算术系统的一种应用,设计了一种使用展位编码算法和冗余代码的高速并行乘法器(通过使用多值MOS电流模式电路来实现)。在正常功耗下,所提出的电路的性能被评估为比相应的二进制实现的性能更快。制造原型芯片以确认多值算术电路的基本操作。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号