A noise-shaping accelerometer interface circuit for two-chip implementation

摘要

A proposed third-order noise-shaping accelerometer interface circuit enhances the SNR, compared with the previously presented interface circuits. The solution for the two-chip implementation is described and a novel cross-coupled CDS integrator is proposed. This scheme functions even with the large parasitic capacitances between the sensor and the interface circuit. The op-amp noise is first-order shaped. Dithering circuit is also implemented on the chip, fabricated in AMI 1.6 /spl mu/m CMOS process.