Electrostatic discharge (ESD) protection in silicon-on-insulator (SOI) CMOS technology with aluminum and copper interconnects in advanced microprocessor semiconductor chips

摘要

This paper discusses the electrostatic discharge (ESD) robustness in silicon-on-insulator (SOI) high-pin- count high-performance semiconductor chips. The ESD results demonstrate that sufficient ESD protection levels are achievable in SOI microporocessors using lateral ESD SOI polysilicon-bound gated diodes without the need for additional masking steps, process implants of ESD design area.