Simulation of self heating effects in heterojunction bipolar transistors fabricated in wafer bonded soi substrates

摘要

Bipolar transistors fabricated on SOI substrates offer the possibility of lower parasitic capacitance, but have a breater susceptibility to self heating. In this paper a simulation of self heating in a SiGe HBT, fabricated on an SOI substrate, is carried out. The importance of establishing appropriate thermal boundary conditions is described. A suitable technique for reducing the rise in temperature is suggested.