A quick literature survey revealed that many researchers have and continue to work on automatic test pattern generation for analog and mixed-signal circuits and systems, however, very few if any have addressed the problem of test set size. This paper presents a novel test set compaction algorithm which takes a generated test set and maximally reduces the number of test vectors required while maximizing the fault coverage. Results show that 58.33% reduction can be achieved. Smaller test set implies lower total test time and long test times have been identified as one of the bottlenecks in analog and mixed-signal test.
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