Design and performance verification of ALUs for 64-bit 8-issue superscaler microprocessors using 0.25 um CMOS technology

摘要

In this paper, we present designs of a set of four non-homogeneous ALUs which can be employed in the next generation 64-bit /spl times/86-compatible microprocessors. The entire design is realized by synthesizable Verilog RTL (register-transfer level) code. The gate level code is generated by Synopsys using COMPASS 0.6 um 1P3M cell library, and UMC 0.25 um 1P5M cell library. The correctness of the functionality of the individual ALU is verified in both RTL code and gate level code after the synthesization.