A realistic power grid and pseudo-random signal lines connected to on-chip drivers are included for accurate extraction of the parasitic inductance in a 5-metal layer 0.25-/spl mu/m CMOS technology. A new ring oscillator for the extraction of signal delay and characteristic impedance is demonstrated. The increase of signal delay due to mutual inductance of clock lines is measured directly with S-parameter characterization techniques.
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机译:包括一个实际的电源网格和连接到片上驱动器的伪随机信号线,以精确提取0.25- / splμm/ m CMOS技术的5金属层中的寄生电感。演示了一种用于提取信号延迟和特性阻抗的新型环形振荡器。由时钟线的互感引起的信号延迟的增加可直接使用S参数表征技术进行测量。
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