On-chip inductance extraction, simulation and modeling.

摘要

As technologies shrink further, operating frequencies increase, and low-k dielectrics are introduced to diminish capacitive effects, on-chip inductance effects become more and more dominant in VLSI circuits. The fast and accurate analysis of inductance is seen as growing problems in recent years. This thesis consists of three parts, covering the extraction, simulation and compact modeling aspects of on-chip inductance issues.; A precorrected-FFT approach for fast and highly accurate simulation of circuits with on-chip inductance is first proposed, with the objective of calculating the product of a dense partial element equivalent circuit (PEEC) inductance matrix and a current vector, an operation with a high computational cost. The effects of all of the inductors are implicitly considered in the calculation. Grid representation of currents enables the use of the discrete Fast Fourier Transform (FFT) for fast magnetic vector potential calculation. In terms of accuracy, memory and speed, it is shown that the precorrected-FFT method is an excellent approach for simulating on-chip inductance in a large circuit.; Next, two practical approaches for on-chip inductance extraction are proposed to obtain a highly sparsified and accurate inverse inductance matrix K. Both approaches use circuit characteristics to obtain a sparse, stable and symmetric K, using the concept of resistance-dominant and inductance-dominant lines. Algorithm 1 is more realistic, while Algorithm 2 works under the simplified assumptions that the supply lines have zero $jLijdIj/dt$ drops and that currents return from a user-defined distance. K-PRIMA, an extension of the reduced-order modeling technique, PRIMA, is developed to handle K matrices with guarantees of passivity.; Finally, a table look-up compact model, two-path ladder model, for RLC interconnect lines is proposed for on-chip interconnect timing and noise analysis. The model parameters are synthesized through constrained nonlinear optimization to directly match the signal response characteristics over a range of input transition times and loads. The effect of capacitances on the return current distribution is explicitly considered. This model is demonstrated to accurately predict responses such as the interconnect delay, gate delay, transition times at near and far ends of switching lines as well as the overshoot at the far ends of switching lines.