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Effect of poly-Si on electromigration behaviors and microstructure characteristics of Au metallization

机译:多晶硅对金金属电迁移行为和微观结构特征的影响

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For BJT and MOSFET, poly-Si is the most critical layer used as an emitter to improve the current gain in BJT and as a gate to improve the gate oxide reliability in MOSFET. In both cases, the poly-Si is then connected to the conductor. It is very imporatant to understand how poly-Si affects the microstructure and the electromigration behavior of conductor. NIST test structures (length=800 #mu#, thickness=0.7#mu#, widths= 1, 5, 10#mu#) with Au conductor and TiW/TiWN/TiW barrier were used to study the impact of poly-Si. Two groups of samples were used: one with poly-Si under the barrier were used to study the impact of poly-Si. Two groups of samples were used: one with poly-Si under the barrier and the other without poly-Si. Thermal oxide was used to isolate the substrate from the conductor and Si_3N_4, was used as passivations. DC stress was performed at 175, 200, and 225 deg. Microbeam X-ray Diffraction (#mu# XRD) was used to characterize the microstructure of the TiW barrier and Au metallization layers as a function of line length and width. The data indicates that samples with poly-Si have lower electromigration resistance for Au conductors for all widths and temperatures, with higher initial deformation fault densities on poly-Si.
机译:对于BJT和MOSFET,多晶硅是最关键的层,用作提高BJT中电流增益的发射极,以及用作提高MOSFET中栅极氧化物可靠性的栅极。在这两种情况下,然后将多晶硅连接到导体。了解多晶硅如何影响导体的微观结构和电迁移行为非常重要。使用具有Au导体和TiW / TiWN / TiW势垒的NI​​ST测试结构(长度= 800#mu#,厚度= 0.7#mu#,宽度= 1、5、10#mu#)来研究多晶硅的影响。使用两组样品:一组在势垒下具有多晶硅的样品用于研究多晶硅的影响。使用了两组样品:一组在阻挡层下带有多晶硅,另一组没有多晶硅。使用热氧化物将衬底与导体隔离,并将Si_3N_4用作钝化层。 DC应力是在175、200和225度下执行的。使用微束X射线衍射(#mu#XRD)来表征TiW势垒层和Au金属化层的微观结构,作为线长和线宽的函数。数据表明,在所有宽度和温度下,含多晶硅的样品对金导体的电迁移电阻较低,而在多晶硅上的初始变形故障密度较高。

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