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Shallow p-type source/drain extension formation using B2H6 plasma doping for deep submicron CMOS

机译:使用B2H6等离子掺杂形成深亚微米CMOS的浅p型源极/漏极扩展层

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Abstract: In this paper, we studied the feasibility of using a commercial etch chamber to perform plasma doping to form shallow p$+$PLU$/-n junction. The plasma doping has the advantage of high wafer throughput compared to conventional low energy implanters. Ultra-shallow boron implantation was done in a plasma reactor with a Helicon plasma source and a gas mixture of He$PLU@B$-2$/H$-6$/. 0.18 micrometer class PMOS devices were fabricated using the plasma doping and compared with devices with a conventional BF$-2$/ S/D extension implant (10 keV BF$-2$/ implant, X$-j$/ approximately equals 650 Angstrom). The key results are as follows. (1) Shallow boron implant with good process uniformity on a wafer was achieved using the plasma doping process. Boron dose of approximately 5E14 cm$+$MIN@2$/ and junction depth (X$-j$/) of approximately 250 Angstrom was achieved after S/D annealing. (2) The pMOS devices fabricated using the plasma doping have much better short channel effect (SCE) characteristics than the devices fabricated with 10 keV BF$-2$/ implant. The improvement of X$- j$/ in the vertical direction of a transistor (from approximately 650 angstrom to approximately 220 angstrom) using the plasma doping resulted in an improvement of approximately 450 angstrom in the lateral direction shown in L$-g$/$+min$/. (3) Degradation in gate-depletion was observed for the plasma doping devices; however, the degradation can be recovered by using an extra gate implant step. (4) Compared to devices with the conventional implant, higher R$-sd$/ was found in devices with the plasma doping process. This higher R$-sd$/ for the B$-2$/H$-6$/ cases was most likely due to the less gate-to-drain overlap and carbon/oxygen contaminants introduced during the plasma doping process. (5) Higher gate- edge diode leakage was also observed in the plasma doping devices. The high diode leakage was believed also due to the contaminants. !6
机译:摘要:在本文中,我们研究了使用商业蚀刻室进行等离子体掺杂来形成浅p $ + $ plu $ / - n交界处的可行性。与传统的低能量注入机相比,等离子体掺杂具有高晶片吞吐量的优点。超浅硼植入是在血浆反应器中进行的,用赫尔米尔血浆源和HE $ PLU的气体混合物 - B $ -2 $ / h $ -6 $ /。使用等离子掺杂制造0.18微米的PMOS器件,与传统的BF $ -2 $ / S / D延长植入物(10 kev bf $ -2 $ /植入物,x $ -j $ /近似等于650 angstrom )。关键结果如下。 (1)使用等离子体掺杂工艺实现晶片上具有良好工艺均匀性的浅硼植入物。在S / D退火后,实现了大约5e14 cm $ + $ min @ 2 $ /和结深度(x $-j $ /),在S / D退火后实现了大约250埃。 (2)使用等离子体掺杂制造的PMOS器件具有比10kev BF $ -2 $ /植入物制造的器件更好的短沟道效果(SCE)特性。使用等离子掺杂的晶体管垂直方向(从大约650埃到大约220埃)的垂直方向的改善导致L $ -g $ /的横向上的大约450埃的提高$ + min $ /。 (3)对等离子体掺杂装置观察到栅极消耗的降解;然而,可以通过使用额外的栅极植入步骤来恢复劣化。 (4)与具有常规植入物的器件相比,在具有等离子体掺杂过程的器件中找到了更高的R $ -SD $ /。这更高的R $ -SD $ /为B $ -2 $ / h $ -6 $ /案例很可能是由于等离子掺杂过程中引入的较少的漏极 - 排水重叠和碳/氧污染物。 (5)在等离子体掺杂装置中也观察到更高的栅极边缘二极管泄漏。由于污染物,也相信高二极管泄漏。 !6

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