Abstract: As channel lengths shrink continuously to smaller dimensions in order to improve performance and packing density, lithography, isolation, power supply and short channel effects have proved to be major limitations. Recently vertical MOSFETs (VMOS), also known as surround gate transistors, or 3-D side- wall transistors have been shown to overcome these process limitations. In this paper, we review the various VMOS technologies and applications and compare the performance of these devices to planar devices. We also present a novel deep submicron vertical SiGe/Si PMOSFET fabricated by Ge implantation. The Ge was implanted in the Si vertical channel to form a strained SiGe layer to increase drive current in P channel devices. PMOS drive current can be increased by about 100% compared to Si control devices. Thus, this technology offers CMOS circuit designers the flexibility to match PMOS and NMOS current drive capabilities, which was previously limited by the difference in electron and hole mobilities in Si. !20
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机译：摘要：随着沟道长度不断缩小到较小的尺寸以提高性能和堆积密度，光刻，隔离，电源和短沟道效应已被证明是主要限制。最近，已经显示出垂直MOSFET（VMOS）（也称为环绕栅晶体管或3-D侧壁晶体管）克服了这些工艺限制。在本文中，我们回顾了各种VMOS技术和应用，并将这些器件的性能与平面器件进行了比较。我们还介绍了一种通过Ge注入制造的新型深亚微米垂直SiGe / Si PMOSFET。将Ge注入Si垂直沟道中以形成应变的SiGe层，以增加P沟道器件中的驱动电流。与Si控制设备相比，PMOS驱动电流可以增加约100％。因此，这项技术为CMOS电路设计人员提供了匹配PMOS和NMOS电流驱动能力的灵活性，而该能力以前受到Si中电子迁移率和空穴迁移率差异的限制。 ！20
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