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Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design

机译:嵌入式系统设计中利用高效DRAM访问模式的变量的内存布局技术

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The delay of memory access is one of the major bottlenecks in embedded systems' performance. In software compilation, it is known that there are high variations in memory access delay depending on the ways of storing/retrieving the variables in code to/from the memories. In this paper, we propose an effective storage assignment technique for variables to maximize the use of memory bandwidth. Specifically, we study the problem of DRAM memory layout for storing the nonarray variables in code to achieve a maximum utilization of page and/or burst modes for the memory accesses. The contributions of our work are, for each of page and burst modes: (1) We prove that the problem is NP-hard; (2) We propose an exact formulation of the problem and efficient memory layout algorithms, called Solve-MLP for the page mode and Solve-MLB for the burst mode; From experiments with a set of benchmark programs, we confirm that our proposed techniques use on average 20.0% and 9.9% more page accesses and 54.0% and 86.6% more burst accesses than those by OFU (the order of first use) and the technique in P.R. Panda et al. (1997), respectively.
机译:内存访问的延迟是嵌入式系统性能的主要瓶颈之一。在软件编译中,众所周知,取决于将代码中的变量存储到存储器中或从存储器中检索出变量的方式,存储器访问延迟存在很大的差异。在本文中,我们提出了一种有效的变量存储分配技术,以最大程度地利用内存带宽。具体来说,我们研究了用于在代码中存储非数组变量的DRAM内存布局问题,以最大程度地利用页面和/或突发模式进行内存访问。对于页面和突发模式,我们所做的工作分别是:(1)我们证明问题是NP难题的; (2)我们提出问题的精确表述和有效的内存布局算法,对于页面模式,称为Solve-MLP;对于突发模式,称为Solve-MLB;通过一系列基准程序的实验,我们确认,与OFU(首次使用的顺序)相比,我们提出的技术平均使用了20.0%和9.9%的页面访问量,而突发访问平均使用了54.0%和86.6%的突发访问量。 PR Panda等。 (1997)。

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