Optoelectronic interconnect architecture of parallel modified signed-digit adder and subtractor

摘要

Abstract: In this paper, a space-position-logic-encoding scheme is proposed, which not only makes best use of the convenience of binary logic operation, but is also suitable for the trinary property of modified signed-digit numbers. Based on the space-position-logic-encoding scheme, a fully parallel modified signed-digit adder and subtracter is built by use of optoelectronic switch and microstructure interconnect technologies. Thus an effective combination of a parallel algorithm and a parallel architecture is implemented. Finally, both simulation results and experimental results are provided. !10