Optoelectronic receivers in silicon on sapphire CMOS: Architecture and design for efficient parallel interconnects.

摘要

Internal data rates of processors fabricated in deep sub-micron CMOS technology have exceeded gigahertz rates. While processing proceeds at gigahertz internally, off chip wires have held inter-chip clock rates in the hundreds of megahertz. The rate of inter-chip communication is now the bottleneck in high performance systems.; Optical inter and intra-chip communication has the potential to solve interconnect problems. Inter-chip opto-electronic communication is complicated by the difficulty of routing bidirectional optical signals in parallel around substrates. Furthermore, the design of CMOS compatible high performance electronics for optical channel interfaces is limited by parasitic effects in today's bulk CMOS processes.; In this dissertation, I focus on approaches to solving the inter-chip communication problem by through opto-electronic receiver design. This approach is multifaceted. First, I will discuss receiver design using the newly developed ultra-thin silicon-on-sapphire CMOS technology. I present designs and results of circuits that exploit both the optical and insulating properties of the sapphire substrate to implement short and middle distance opto-electronic links. Interconnects constructed in this way avoid conventional CMOS routing and speed limitations. Second, I will consider various receiver architectures for power efficient short and middle distance bit transfer in the context of an optical link. Finally, I will discuss scanned and spike-based data transfer of continuous valued data arrays. By examining the problem of optoelectronic receiver design from three angles, I hope to promote a deeper understanding of the overlapping issues concerned in design of highly connective systems for the future of CMOS electronics.