MAIN: Multiprocessor Architecture for Image Compression

摘要

This paper presents a DSP-based parallel implementation intended for image compression. The basic processing module is built around the Texas Instruments TMS 320C25 digital signal processor (DSP). In this system the DSPs work in a parallel mode upon a divided image. Currently, the system is intended to perform compression of 256/spl times/256 8-bit images and can be easily adapted to work upon greater image sizes. Its modular design makes it expandable and allows to obtain real-time compression operation. The use of programmable DSPs permits the improvement and the partial/total change of the compression algorithm. Separate low-pass and high-pass image coding is used in the compression process. Compression ratio is dynamically adaptable and allows us to select the quality of the reconstructed images.