An integrated functional tester for CMOS logic

摘要

This paper presents the architecture of a functional tester system based on a functional tester chip (FTC) featuring per-pin programmability, output waveform formatting (NR, RC, RH, and RL), input window comparison and on-the-fly format switching. Waveforms are encoded using a set of simple 8-bit instructions. The bandwidth requirements of each channel is 8 bits per test vector. A four-channel FTC implemented using digital standard cells, with a 1.2 micron dual metal layer CMOS process, has a die size of 7/spl times/6 mm/sup 2/ (core: 6/spl times/5 mm/sup 2/). Each channel occupies approximately 17% of the core area. Almost half the channel area is used by the format memory which provides a cache of the required timing and formats for a given test. Preliminary results based on measurements from an early version of the wave formatting circuit suggest that edge resolutions of at least 1.5 ns are possible.