A multi-layer interconnect model for mega bit BiCMOS SRAMs is developed. The model is based on interconnection resistance, capacitance, and inductance associated with the BiCMOS SRAM cell. The interconnect effect on SRAM device performance parameters, propagation delay, speed, power consumption, and noise parameters are analyzed. A case study is presented for 1-Mb BiCMOS SRAM chip interconnection problems.
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