A BiCMOS SRAM generator for ASIC applications.

摘要

A BiCMOS SRAM generator which is applicable to 64 k - 1 Mbit with 4 bits/word - 64 bits/word is developed for ASIC applications in this dissertation. A BiCMOS technology file and a NPN device generator are created to design BiCMOS circuits. A method of using the GPD Lx application in Mentor Graphic GDT to generate the layout/schematic of an NPN transistor in a BiCMOS process is developed. This method can be used to generate any customized device. A new comparison method is developed to compare the speed of a BiCMOS driver with that of a CMOS driver. In this method, the difference in output swing between a CMOS circuit and a BiCMOS circuit is considered. Therefore, this new method is more accurate than the "normalized" comparison method used by most circuit designers. A GWL BiCMOS decoder/driver and a LWL BiCMOS decoder/driver are designed. The X decoding time is reduced to 1.4 ns (for the worst case) by using the drivers designed. A sensing time of about 1.06 ns is achieved by using the cascode bipolar sense amplifier designed in this research. The memory sizing design and the memory layout design are carried out to achieve very small memory cell area ({dollar}10times 16.1 mu{lcub}rm m{rcub}sp2).{dollar} The memory cell is designed in such a way that the bit lines in the cell run in metal 2 vertically and the GWL line runs in metal 3 horizontally, while the LWL line runs in metal 1 horizontally. A memory core subgenerator, a GWL decoder/driver subgenerator and a 2 stage sense amplifier subgenerator are designed using the "add{dollar}sb-{dollar}array" function, the "add{dollar}sb-{dollar}instance" function and the sliced method specially developed in this research. A 0.8 {dollar}mu{dollar}m process with 5 V power supply is used in this research.