A new approach for teaching computer engineering laboratory using PLDS2

摘要

A brief overview of a development system, the Altera PLDS2 (programmable logic development system), is presented. The use of the PLDS2 in a laboratory course for digital logic design is reported to have made it possible for students to choose between TTL and CMOS-based EPLDs on the basis of cost effectiveness. The Altera PLDS2 is a complete hardware and software development system that enables the circuit designer (students) to develop an optimized code for programming the 'target' Altera EPLDs. The system allows various design input techniques for different logic design tasks. These inputs include schematic capture, netlist entry, Boolean-equations entry, and state-machine entry. Students are not restricted to just one entry method but may 'mix and match' methods to best meet the needs of the overall logic design.