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Design and Demonstration of Single and Coupled Embedded Toroidal Inductors for 48V to 1V Integrated Voltage Regulators

机译:用于48V至1V集成稳压器的单耦合耦合环形电感器的设计和演示

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High-efficiency High-Voltage Integrated Voltage Regulators (HV-IVR) will allow the next generation of data centers and servers to operate with higher efficiency while delivering more computing power. High-density embedded inductors operating at frequencies over 10 MHz allows the miniaturization of power modules enabling their integration closer to the SoC. However, single stage 48V to 1V IVR present new challenges that are not seen in low voltage converter such as 3.3V or 1.7V to 1V. In this work, a novel expandable interleaved toroidal inductor cell with vias-in-slot thru magnetic sheet is presented. In addition, we present a new metric for magnetic material and inductor technologies to describe their efficiency under different duty cycle conditions. Using the analysis of two available magnetic sheets with permeability 50 and 150 at 10MHz, we present the magnetic properties of a magnetic sheet to obtain 95% of inductor efficiency, an inductance density of 113 nH/mm3 at 10 MHz, a saturation current over 2.5A, and DC resistance around 20 mΩ. These inductor requirements are given by the possible power stage topologies that can be used to achieve 48V to 1V, where some of them use single inductor while others use coupled or tapped inductors. The efficiency conditions for the inductor presented in this work must be matched by the power stage topology, leading to a co-design between power inductor and the power stage topology. In this work we present why the duty cycle must be extended by a factor of 4 in order to obtain a 95% efficiency in the inductor. We provide a process for the fabrication of these inductors. Finally, a test inductor is fabricated that shows an inductance density of 77 nH/mm3 and correlates well with the simulation model. This allows to predict with good accuracy the inductor performance with the proposed inductor design and magnetic sheet properties.
机译:高效高压集成稳压器(HV-IVR)将使下一代数据中心和服务器以更高的效率运行,同时提供更多的计算能力。以高于10 MHz的频率工作的高密度嵌入式电感器可使电源模块小型化,从而使其集成度更接近SoC。但是,单级48V至1V IVR提出了新挑战,这在低压转换器中是看不到的,例如3.3V或1.7V至1V。在这项工作中,提出了一种新颖的可扩展交错式环形电感器单元,该单元带有通孔磁通片。此外,我们提出了一种针对磁性材料和电感器技术的新指标,以描述其在不同占空比条件下的效率。通过对两个可用磁导率分别为50和150,在10MHz的磁性薄板进行分析,我们得出了磁性薄板的磁性能,以获得95%的电感效率,电感密度为113 nH / mm 3 在10 MHz时,饱和电流超过2.5A,直流电阻约为20mΩ。这些电感器要求由可用于实现48V至1V的功率级拓扑结构给出,其中一些使用单个电感器,而另一些使用耦合或抽头电感器。这项工作中提出的电感器的效率条件必须与功率级拓扑相匹配,从而导致功率电感器和功率级拓扑之间的共同设计。在这项工作中,我们介绍了为什么必须将占空比延长4倍才能在电感器中获得95%的效率。我们提供了制造这些电感器的过程。最后,制造出一个测试电感,其电感密度为77 nH / mm 3 并与仿真模型很好地相关。这样就可以通过拟议的电感器设计和磁性片特性,以很高的精度预测电感器性能。

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