Innovative dual mark design for alignment verification and process monitoring in advanced lithography

摘要

Improving on product overlay is one of the key challenges when shrinking technology nodes in semiconductor manufacturing. Using information from non-lithography process steps can unleash overlay improvement potential.1 The challenge is to find intra-wafer signatures by measuring planar distortion. Several previous applications showed that using exposure tool wafer alignment data can improve overlay performance.2 With smart placement of alignment mark pairs in the X and Y direction, it is possible to determine intra-wafer distortion wafer-by-wafcr. Both the measurement and modeled results are applied directly as a feed-forward correction to enable wafer level control. In this paper, the capability to do this is evaluated in a feasibility study.