Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations

摘要

Efficient fault simulation algorithms for combinational circuits are known for decades. However, sequential fault simulation which is frequently used in test and fault tolerance applications remains a very time-consuming task, in particular for larger circuits. Current paper proposes a new deductive method for Register-Transfer Level (RTL) fault simulation on the system model of high-level decision diagrams. We apply the bit coverage fault model which has proven to provide a good correspondence with gate-level structural faults. Simulation speed-up is achieved due to efficient data structures implemented to perform set operations in the deductive fault simulation algorithm. Experiments on RTL benchmark circuits show that up to two orders of magnitude shorter run-times are achieved with the method in comparison to gate-level fault simulation.