Modeling and Optimization of a Microprobe Detector for Area and Yield Improvement

摘要

Common physical attacks in integrated circuits make use of microprobes to sense information in specific bus lines. It can be mitigated with additional built-in circuitry to detect deviations in the expected capacitance of the bus lines caused by these attacking probes. The strategy is to convert capacitance deviations into delay deviations, followed by time-to-digital conversion to provide a signature that is used to identify a probe attack. However, the sensitivity to delay deviation is highly related to individual sizes of elements that compose the protecting circuit. In this paper, a multi-objective optimization-based methodology is applied to optimize the required silicon area as well as the robustness and parametric manufacturing yield of a microprobe detector. We present the required computational modeling of the circuit optimization objectives and constraints for a successful application of optimization methods. Results show that this approach reduces the required circuit gate area up to 50% compared to manual sizing, while guaranteeing high manufacturing yield.