High-Speed 32*32 bit Multiplier in 0.18um CMOS Process

摘要

In this paper, a new high-speed and low power unsigned multiplication structure is proposed: based on the proposed algorithm, the input bits of multiplier are broken into several smaller groups of bits and the multiplication of them are calculated concurrently. The final product of multiplication is generated after several rounds of the small group's results aggregation. A 32*32-bit multiplier according to the proposed structure is designed in 0.18um CMOS process. The overall delay of 32*32-bit multiplier is extremely low and is only 2.1ns. The power consumption is 41mW.