Design of Low-Area and High Speed Pipelined Single Precision Floating Point Multiplier

摘要

Floating point multiplication is a common operation in advance Digital Signal Processing (DSP) applications. This paper explains a 32-bit binary Floating Point Multiplier (FPM) architecture using an area efficient array multiplier. The proposed multiplier generates only the needed MSB bits of the product mantissa by making use of Divide and Conquer (D&C) algorithm with a modified Full Adder (FA) to increase the speed of multiplication. The pipeline architecture is also proposed to improve the performance of the multiplication in terms of reduced delay and power. The proposed FPM is compared with booth recoding based FPM and the various performance measures such as area, power and delay are analyzed.