High Speed IEEE-754 Quadruple Precision Floating Point Multiplier Using Verilog

摘要

Floating Point (FP) multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. Quadruple, double, and single precision floating point multipliers are implemented using conventional, Canonical Signed Digit (CSD), Vedic, and radix-4 Booth multiplier methods using Verilog language and ported on Xilinx Virtex-5 (5vlx50ff1153-3) FPGA. In addition, the proposed design is compliant with IEEE-754 format and handles rounding conditions. The quadruple precision floating point multiplier designs achieved the operating frequency of 12.13, 7.39, 4.1, and 18.94 MHz with an area of 6434, 13339, 20449, and 6309 slices respectively. Quadruple precision floating point multiplier using radix-4 Booth multiplier method provides less area and high speed compared to other three methods.