UVM-based Verification of a Digital PLL Using SystemVerilog

摘要

One of the most significant trends in the semiconductor industry is mixed-signal applications. A great amount of effort is focused on creating fast and accurate designs, which include both analog and digital components. As a result, mixed-signal verification poses a major concern. Previous traditional verification techniques offer slow verification time and relatively small robustness. In this work, an efficient UVM-based verification architecture for a digital phase-locked loop (DPLL) real number model using SystemVerilog is presented. The UVM capabilities of the proposed methodology combined with the RNM model of the digital PLL favors the generation of a reusable, time-to-market fast and robust verification environment. Cadence Incisive Enterprise Simulator was used for the testbench creation and simulation. The proposed verification architecture uses constrained-random stimulus generation, analog assertions and coverage metrics, in order to achieve high gains in verification efficiency.