Power Surge and Clock Hiccup Side-Channel Watermarking Approach for Finite State Machines

摘要

We propose two watermarking techniques, one with power side-channel detection and another with clock hiccup side-channel detection. Hidden watermarking tags will be im-plemented by merging a watermark FSM into the design FSM with a side-channel leakage component in the form of power surge or clock hiccup. In some previously proposed approaches watermark states are merged into the design FSM by utilizing the unused states and/or transitions in the design FSM. Our approach, by designing the watermark FSM separately, allows a certain degree of automation, and reduced power consumption. In our approach, the design FSM is not modified at all and it keeps operating even when the watermark FSM is triggered. The watermark FSM is triggered only when the design FSM reaches a secret designated state, and only when the entire digital signature bit sequence is accepted as the input will the final watermark matching state be reached. This state will trigger the side-channel leakage unit, thus verifying the existence of the watermark and ownership. A purely side-channel based approach will make functional analysis based attacks quite difficult.