Design and Evaluation of a Wafer-level Probe Solution of High Current Step-down DC-DC Converter for Test Time Reduction, Yield Improvement and Overall Test Cost Reduction

摘要

For integrated circuits (IC) electrical testing, measurement of high current parameters is usually done on a packaged-level. In this paper, the design and evaluation results of a wafer-level probe solution for a high current step-down DC-DC converter are presented. The full turn-key, hardware and software development of probe solution was implemented. The buck converter used has a device specification maximum of 7 Amperes. Upon the series of experiments and evaluations, the probe wafer with more than 15000 dies has a probe yield of greater than 97%. The average process capability index (Cpk) per main test block is greater than 1.67 for both 200-sample and one-wafer datasets. To add, the basic electrical parameters of a step-down DC-DC converter such as shutdown supply current, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) on resistance and the current limit threshold were tested and measured using an Automatic Test Equipment (ATE), and have readings well within the specification limits. With this wafer-level probe solution, the defects were screened out at an early stage before performing IC assembly processes. Since test coverage is now moved to a wafer-level with minimal coverage on assembled package-level, the solution brought about to 6% test time reduction, and 0.6% improvement on assembled-level test yield, thus reduced the overall test cost.