A 12bit 16MS/s Asynchronous SAR ADC with Speed-Enhanced Comparator and TSPC Latch

摘要

this paper presents a 12bit 16MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) with a speed-enhanced comparator and true single-phase-clock (TSPC) latch. An additional positive feedback loop is applied to the comparator to increase the comparator speed. Moreover, the use of TSPC latch reduces the load on the comparator and decreases the delay of the SAR LOGIC to the DAC. This paper also introduces a method of implementing a variable delay unit. The proposed ADC was simulated in SMIC one-poly-eight-metal (1P8M) 130nm CMOS technology. At a 3.3V supply, the ADC achieves an SNDR of 70.8dB and consumes 4.95mW. The peak DNL error is +0.25/-0.25LSB, and the peak INL is +1.1/ -0.8LSB.