CMOS Implementation of Comparators for ADCs

摘要

Recent advances as well as new innovations in IC technology and circuit design techniques have lead to design systems that can entirely replace complex analog signal with digital Dynamic comparators are reasonable for ADCs with superior because of low power utilization and quick speed. Be that as it may, when CMOS technology forms into a profound submicron to improve the comparator's speed and power utilization, the kick-back noise and offset are fundamentally more awful and influence the comparator's execution. To make the comparator increasingly accurate, the technique for decreasing kick-back noise and aligning the offset voltage ought to be included. Another dynamic comparator was proposed to diminish the kickback noise and align the offset voltage. In this work, both the existing Comparator Architectures and Proposed Comparator Architectures are designed and simulated in Mentor Graphics Design Tools with 130 nm Technology.