IC layout weak point effectiveness evaluation based on statistical methods

摘要

Design hotspots, a.k.a. layout weak points are layout patterns that are susceptible to systematic failure and yield loss in high-volume manufacturing (HVM). Therefore, understanding the yield impact of layout weak point is a crucial step for yield learning. Layout weak points can be identified by layout analysis based on simulation or silicon learning from past failures. In advanced technology nodes, the interaction between design and manufacturing process is increasingly significant, making it paramount to quantify which layout weak points are causing yield loss for a specific manufacturing process. This can be achieved by collecting volume scan diagnosis results and then map the call-outs to suspected weak points for defect root-cause analysis. One major challenge in this process is the often-false assumptions that correlation is causation, especially as scan diagnosis resolution is typically not ideal and random correlation hits can be common as the weak point count grows. In this work, we propose a novel approach for quantitatively assessing the impact of layout weak points on IC failure using statistical methods. We develop a new weak point effectiveness metric to help guide the decision on whether a specific weak point is a root cause in a population of volume scan diagnosis results. Experimental results show that our approach is able to interpret high count weak points for “meaningful” root-cause and rank the relative contribution of different weak point sets.