Systematic b-adjacent symbol error correcting reed-solomon codes with parallel decoding

摘要

With technology scaling, the probability of write disturbances affecting neighboring memory cells in nonvolatile memories is increasing. Multilevel cell (MLC) phase change memories (PCM) specifically suffer from such errors which affects multiple adjacent memory cells. Reed Solomon (RS) codes offer good error protection since they can correct multi-bit symbols at a time. But beyond single symbol error correction, the decoding complexity as well as the decoding latency is very high. This paper proposes a systematic b-adjacent symbol error correcting code based on Reed-Solomon codes with a low latency and low complexity parallel one step decoding scheme. A general code construction methodology is presented which can correct any errors within b-adjacent symbols. The proposed codes are compared to existing adjacent symbol error correcting Reed-Solomon codes, and it is shown that the proposed codes achieve better decoder latency. The proposed codes are also shown to achieve much better redundancy compared to symbol error correcting orthogonal Latin square (OLS) codes.