A 1–60 GHz 9.6 mW 0.18 V Output-Swing Static Clock Divider Circuit in 45-nm SOI CMOS

摘要

This paper reports on a cross-coupled latch-based static clock divider circuit with a wide frequency division range. Detailed circuit level design for wideband operation of the clock divider is discussed and insightful measurement results are reported. These include output divided clock power levels, output clock jitter, eye diagrams, and the sensitivity plot of the clock divider. Designed in 45-nm CMOS, the clock divider is measured to have a frequency division range of 1-60 GHz, moderate power consumption of 9.6 mW and among the best energy figures compared to the reported clock dividers.