Slicing FIFOs for on-chip memory bandwidth exhaustion

摘要

Within an MPSoC environment, the delivery of data from one computation stage to the next is often the bottleneck of the overall system performance. Especially in high-speed communication where at least two actors (producer and consumer) need access to the same data, the memory interface is usually the limiting factor. Therefore, many solutions like network on chips, clusters of shared memory, memory hierarchy, etc. have been proposed to transfer data from one actor to another. To avoid using dual port memory macros-which are expensive in terms of chip area-we propose a hardware design where the communication through FIFOs is transparently sliced to a multitude of altering memory banks. This allows simultaneous memory accesses to the same FIFO while using only single port memory macros, thus reducing on-chip area and access delay.