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2000 Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler

机译：2000在VIRAM编译器中利用片上存储器带宽

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David Judd; Katherine Yelick; Christoforos Kozyrakis; David Martin; David Patterson;
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年度 2008
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1. A Compiler Approach to Managing Storage and Memory Bandwidth in Configurable Architectures [J] . NASTARAN BARADARAN, PEDRO C. DINIZ ACM Transactions on Design Automation of Electronic Systems . 2008,第4期

机译：在可配置体系结构中管理存储和内存带宽的编译器方法
2. Slicing FIFOs for On-Chip Memory Bandwidth Exhaustion [J] . Hasler Mattis, Wittig Robert, Matus Emil, IEEE transactions on circuits and systems . I , Regular papers . 2020,第2期

机译：切片FIFO用于片上内存带宽耗尽
3. Improving the performance of GPU-based genetic programming through exploitation of on-chip memory [J] . Chitty Darren M. Soft computing: A fusion of foundations, methodologies and applications . 2016,第2期

机译：通过利用片上存储器来提高基于GPU的遗传编程的性能
4. Exploiting On-chip Memory Bandwidth in the VIRAM Compiler [C] . David Judd, Katherine Yelick, Christoforos Kozyrakis, 2nd International Workshop on Intelligent Memory Systems IMS 2000, 2nd, Nov 12, 2000, Cambridge, MA, USA . 2000

机译：在VIRAM编译器中利用片上存储器带宽
5. Compiler and microarchitecture mechanisms for exploiting registers to improve memory performance. [D] . Postiff, Matthew Allan. 2001

机译：用于利用寄存器改善内存性能的编译器和微体系结构机制。
6. Increased space-bandwidth product in pixel super-resolved lensfree on-chip microscopy [O] . Alon Greenbaum, Wei Luo, Bahar Khademhosseinieh, -1

机译：像素超分辨无透镜片上显微镜中增加的空间带宽乘积
7. Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs [O] . Koji Inoue, Koji Kai, Kazuaki Murakami 1999

机译：动态可变线大小缓存利用合并DRam /逻辑LsI的高片上存储器带宽
8. Exploiting Bandwidth to Reduce Average Memory Access Time in ScalableMultiprocessors [R] . Bianchini, R. 1995

机译：利用带宽减少scalablemultiprocessors中的平均内存访问时间

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